The invention relates to a circuit arrangement for a synchronous forward/backward binary counter having a counting direction that can be changed over via a directional control signal and having a chain of D flip-flops, to each of which is assigned at least from the second flip-flop in the chain an individual combinatorial network receiving at least a first and a second state signal, whose values are determined by states of the preceding flip-flops, this network supplying, depending upon these state signals and the directional control signal, to the D input of the assigned flip-flop either its non-inverted output signal or its inverted output signal.
Such a circuit arrangement is known from Japanese Patent Application No. 55-166701 (publication No. 57-91034). In this known circuit arrangement, each combinatorial network has two AND gates, an OR gate and an EXCLUSIVE OR gate. The state signals are the output signals of the flip-flops preceding in the chain so that the number of state signals increases from stage to stage and the AND gates must have correspondingly a larger number of inputs. In longer counters this leads to a considerable amount of wiring and voluminous AND gates, which involves difficulties in the case of a construction as an integrated circuit.
For the realization of gates and flip-flops, different techniques are known, for example the bipolar TTL technique or the CMOS technique using field effect transistors. These techniques are distinguished, for example, by their switching speed and more particularly by their power consumption. With the known techniques, particular diffulcities are not involved in constructing different kinds of combinatorial gates.
A certain exception in this respect is the I.sup.2 L (Integrated Injection Logic) technique, in which only NAND gates can be realized. Other types of combinatorial gates can be derived therefrom, for example by means of inverters, but this requires a considerable amount of labor. If consequently the aforementioned known circuit arrangement should be realized in I.sup.2 L technique in this manner, each combinatorial network becomes very voluminous.